1. Field of Invention
The present invention is directed to an external memory interface that enables devices such as application specific integrated circuit (“ASIC”) devices to read and write data to and from different memory devices having different configurations.
2. Description of Related Art
Certain memory devices, such as quad data rate synchronous random access memory devices, (“QDR SRAMs”), are high-speed memory devices that are capable of, inter alia, supporting balanced read and write cycles to thereby transfer data at a higher frequency than conventional memory devices. Currently, QDR memory devices are available in several different varieties, such as QDR-I (first-generation) and QDR-II (second-generation) that have different configurations such as different data transfer frequencies and data valid windows. In addition, different bus-widths are available for QDR devices, such as 8-bit, 16-bit and 32-bit bus widths.
Due to the various different QDR devices available, there is a need to provide support for transferring data between the many different varieties of QDR devices and a given ASIC device. This will allow products that incorporate ASIC devices to interface with either “wide” memory devices having wide data bus configuration for high performance applications, or “narrow” memory devices with narrower bus widths at a lower cost. For instance, with specific regard to QDR memory devices, QDR-I devices can be used if they are more cost-effective and readily available than QDR-II devices, or vice versa. By supporting both devices, using QDR-I devices that are plentiful now but may be phased out of manufacture later will not make the ASIC device obsolete, since QDR-II devices can be used instead.
Supporting data transfer between the different incarnations of memory devices and an ASIC device can complicate the design of a memory interface in more than one way. For instance, QDR-II devices output read data at a later time than QDR-I devices do, so an interface that supports both QDR-I and QDR-II devices must be able to distinguish the different types of data and accommodate the timing difference. Additionally, in order to accommodate different memory devices having different data bus configurations, some of which do not match the bus configurations of the coupled ASIC, an interface between the memory device and an ASIC device (or an interface section built into the ASIC device) must be able to accurately transfer data between the memory device and the ASIC device without losing any of the data in the process.